?2002 fairchild semiconductor corporation october 2002 FQP45N03L rev. b FQP45N03L FQP45N03L n-channel logic level pwm optimized power mosfet general description this device employs a new advanced mosfet technology and features low gate charge while maintaining low on- resistance. optimized for switching applications, this device improves the overall efficiency of dc/dc converters and allows operation to higher switching frequencies. applications ? dc/dc converters features fast switching r ds(on) = 0.014 ? (typ), v gs = 10v r ds(on) = 0.020 ? (typ), v gs = 5v q g (typ) = 13nc, v gs = 5v q gd (typ) = 4.5nc c iss (typ) = 1450pf mosfet maximum ratings t c = 25c unless otherwise noted thermal characteristics package marking and ordering information symbol parameter ratings units v dss drain to source voltage 30 v v gs gate to source voltage 16 v i d drain current 41 a continuous (t c = 25 o c, v gs = 10v) continuous (t c = 100 o c, v gs = 4.5v) 22 a continuous (t c = 25 o c, v gs = 10v, r ja = 43 o c/w) 8.1 a pulsed figure 4 a p d power dissipation derate above 25 o c 53 0.43 w w/ o c t j , t stg operating and storage temperature -55 to 150 o c r jc thermal resistance junction to case to-220 2.31 o c/w r ja thermal resistance junction to ambient to-220 62 o c/w device marking device package reel size tape width quantity FQP45N03L FQP45N03L to-220ab tube n/a 50 to-220ab drain (flange) drain source gate s g d
?2002 fairchild semiconductor corporation FQP45N03L rev. b FQP45N03L electrical characteristics t c = 25c unless otherwise noted off characteristics on characteristics dynamic characteristics switching characteristics (v gs = 4.5v) switching characteristics (v gs = 10v) unclamped inductive switching drain-source diode characteristics symbol parameter test conditions min typ max units b vdss drain to source breakdown voltage i d = 250 a, v gs = 0v 30 - - v i dss zero gate voltage drain current v ds = 25v - - 1 a v gs = 0v t c = 150 o c- - 250 i gss gate to source leakage current v gs = 16v - - 100 na v gs(th) gate to source threshold voltage v gs = v ds , i d = 250 a1-3v r ds(on) drain to source on resistance i d = 41a, v gs = 10v - 0.014 0.018 ? i d = 22a, v gs = 4.5v - 0.020 0.025 c iss input capacitance v ds = 15v, v gs = 0v, f = 1mhz -1450- pf c oss output capacitance - 300 - pf c rss reverse transfer capacitance - 120 - pf q g(tot) total gate charge at 10v v gs = 0v to 10v v dd = 15v i d = 22a i g = 1.0ma 25 38 nc q g(5) total gate charge at 5v v gs = 0v to 5v - 13 20 nc q g(th) threshold gate charge v gs = 0v to 1v - 1.5 2.3 nc q gs gate to source gate charge - 4.3 - nc q gd gate to drain ?miller? charge - 4.5 - nc t on tur n -o n t im e v dd = 15v, i d = 11a v gs = 5v, r gs = 11 ? --115ns t d(on) tur n -o n d e lay ti me - 15 - ns t r rise time - 60 - ns t d(off) turn-off delay time - 25 - ns t f fall time - 30 - ns t off turn-off time - - 83 ns t on tur n -o n t im e v dd = 15v, i d = 11a v gs = 10v, r gs = 11 ? --57ns t d(on) tur n -o n d e lay ti me - 8 - ns t r rise time - 30 - ns t d(off) turn-off delay time - 45 - ns t f fall time - 30 - ns t off turn-off time - - 115 ns t av avalanche time i d = 2.9a, l = 3.0mh 195 - - s v sd source to drain diode voltage i sd = 22a - - 1.25 v i sd = 20a - - 1.0 v t rr reverse recovery time i sd = 22a, di sd /dt = 100a/ s- - 65 ns q rr reverse recovered charge i sd = 22a, di sd /dt = 100a/ s - - 100 nc
?2002 fairchild semiconductor corporation FQP45N03L rev. b FQP45N03L typical characteristic t c = 25c unless otherwise noted figure 1. normalized power dissipation vs ambient temperature figure 2. maximum continuous drain current vs case temperature figure 3. normalized maximum transient thermal impedance figure 4. peak current capability t a , ambient temperature ( o c) power dissipation multiplier 0 0 25 50 75 100 150 0.2 0.4 0.6 0.8 1.0 1.2 125 0 10 20 30 40 50 25 50 75 100 125 150 i d , drain current (a) t c , case temperature ( o c) v gs = 5v v gs = 10v 0.1 1 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 0.01 2 t , rectangular pulse duration (s) z jc , normalized thermal impedance notes: duty factor: d = t 1 /t 2 peak t j = p dm x z jc x r jc + t c p dm t 1 t 2 0.5 0.2 0.1 0.05 0.01 0.02 duty cycle - descending order single pulse 100 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 40 700 i dm , peak current (a) transconductance may limit current in this region t c = 25 o c i = i 25 150 - t c 125 for temperatures above 25 o c derate peak current as follows: v gs = 5v t, pulse width (s) v gs = 10v
?2002 fairchild semiconductor corporation FQP45N03L rev. b FQP45N03L figure 5. transfer characteristics figure 6. saturation characteristics figure 7. drain to source on resistance vs gate voltage and drain current figure 8. normalized drain to source on resistance vs junction temperature figure 9. normalized gate threshold voltage vs junction temperature figure 10. normalized drain to source breakdown voltage vs junction temperature typical characteristic t c = 25c unless otherwise noted (continued) 0 20 40 60 80 100 123456 i d , drain current (a) v gs , gate to source voltage (v) pulse duration = 80 s duty cycle = 0.5% max v dd = 15v t j = -55 o c t j = 150 o c t j = 25 o c 0 40 80 120 00.51.01.52.0 i d , drain current (a) v ds , drain to source voltage (v) pulse duration = 80 s duty cycle = 0.5% max v gs = 3v t c = 25 o c v gs = 10v v gs = 5v v gs = 4v 20 30 40 246810 10 i d = 22a v gs , gate to source voltage (v) i d = 41a r ds(on) , drain to source on resistance (m ? ) pulse duration = 80 s duty cycle = 0.5% max 0.5 1.0 1.5 2.0 -80 -40 0 40 80 120 160 normalized drain to source t j , junction temperature ( o c) on resistance v gs = 10v, i d = 41a pulse duration = 80 s duty cycle = 0.5% max 0.4 0.6 0.8 1.0 1.2 -80 -40 0 40 80 120 160 normalized gate t j , junction temperature ( o c) v gs = v ds , i d = 250 a threshold voltage 0.9 1.0 1.1 1.2 -80 -40 0 40 80 120 160 t j , junction temperature ( o c) normalized drain to source i d = 250 a breakdown voltage
?2002 fairchild semiconductor corporation FQP45N03L rev. b FQP45N03L figure 11. capacitance vs drain to source voltage figure 12. gate charge waveforms for constant gate currents figure 13. switching time vs gate resistance figure 14. switching time vs gate resistance typical characteristic t c = 25c unless otherwise noted (continued) 100 1000 0.1 1 10 2000 30 c, capacitance (pf) v ds , drain to source voltage (v) v gs = 0v, f = 1mhz c iss = c gs + c gd c oss ? c ds + c gd c rss = c gd 0 2 4 6 8 10 0102030 v gs , gate to source voltage (v) q g , gate charge (nc) v dd = 15v i d = 41a i d = 22a waveforms in descending order: 0 50 100 150 0 1020304050 switching time (ns) r gs , gate to source resistance ( ? ) v gs = 4.5v, v dd = 15v, i d = 11a t d(off) t r t f t d(on) 0 50 100 150 200 0 1020304050 switching time (ns) r gs , gate to source resistance ( ? ) v gs = 10v, v dd = 15v, i d = 11a t d(off) t d(on) t f t r test circuits and waveforms figure 15. unclamped energy test circuit figure 16. unclamped energy waveforms t p v gs 0.01 ? l i as + - v ds v dd r g dut vary t p to obtain required peak i as 0v v dd v ds bv dss t p i as t av 0
?2002 fairchild semiconductor corporation FQP45N03L rev. b FQP45N03L figure 17. gate charge test circuit figure 18. gate charge waveforms figure 19. switching time test circuit figure 20. switching time waveforms test circuits and waveforms (continued) r l v gs + - v ds v dd dut i g(ref) v dd q g(th) v gs = 1v q g(5) v gs = 5v q g(tot) v gs = 10v v ds v gs i g(ref) 0 0 q gs q gd v gs r l r gs dut + - v dd v ds v gs t on t d(on) t r 90% 10% v ds 90% 10% t f t d(off) t off 90% 50% 50% 10% pulse width v gs 0 0
?2002 fairchild semiconductor corporation FQP45N03L rev. b FQP45N03L pspice electrical model .subckt FQP45N03L 2 1 3 ; rev october 2002 ca 12 8 8e-10 cb 15 14 1e-9 cin 6 8 1.35e-9 dbody 7 5 dbodymod dbreak 5 11 dbreakmod dplcap 10 5 dplcapmod ebreak 11 7 17 18 31.8 eds 14 8 5 8 1 egs 13 8 6 8 1 esg 6 10 6 8 1 evthres 6 21 19 8 1 evtemp 20 6 18 22 1 it 8 17 1 ldrain 2 5 1e-9 lgate 1 9 6.24e-9 lsource 3 7 3.15e-9 mmed 16 6 8 8 mmedmod mstro 16 6 8 8 mstromod mweak 16 21 8 8 mweakmod rbreak 17 18 rbreakmod 1 rdrain 50 16 rdrainmod 2e-3 rgate 9 20 1.9 rldrain 2 5 10 rlgate 1 9 62.4 rlsource 3 7 31.5 rslc1 5 51 rslcmod 1e-6 rslc2 5 50 1e3 rsource 8 7 rsourcemod 9.5e-3 rvthres 22 8 rvthresmod 1 rvtemp 18 19 rvtempmod 1 s1a 6 12 13 8 s1amod s1b 13 12 13 8 s1bmod s2a 6 15 14 13 s2amod s2b 13 15 14 13 s2bmod vbat 22 19 dc 1 eslc 51 50 value={(v(5,51)/abs(v(5,51)))*(pwr(v(5,51)/(1e-6*160),5))} .model dbodymod d (is = 1.1e-11 n=1.075 rs = 8.9e-3 trs1 = 9e-4 trs2 = 1e-6 xti=2.2 cjo = 7e-10 tt = 8e-11 m = 0.49) .model dbreakmod d (rs = 1.1 trs1 = 1e-3 trs2 = -8.9e-6) .model dplcapmod d (cjo = 4.5e-10 is = 1e-30 n = 10 m = 0.46) .model mmedmod nmos (vto = 1.9 kp = 6 is=1e-30 n = 10 tox = 1 l = 1u w = 1u rg = 1.9) .model mstromod nmos (vto = 2.29 kp = 50 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u) .model mweakmod nmos (vto = 1.54 kp = 0.05 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u rg = 19 rs = 0.1) .model rbreakmod res (tc1 = 1e-3 tc2 = -7e-7) .model rdrainmod res (tc1 = 1.9e-2 tc2 = 3e-5) .model rslcmod res (tc1 = 1e-3 tc2 = 1e-6) .model rsourcemod res (tc1 = 1e-3 tc2 = 1e-6) .model rvthresmod res (tc1 = -2.1e-3 tc2 = -1e-5) .model rvtempmod res (tc1 = -1.8e-3 tc2 = 1e-6) .model s1amod vswitch (ron = 1e-5 roff = 0.1 von = -4.0 voff= -0.8) .model s1bmod vswitch (ron = 1e-5 roff = 0.1 von = -0.8 voff= -4.0) .model s2amod vswitch (ron = 1e-5 roff = 0.1 von = -0.3 voff= 0.2) .model s2bmod vswitch (ron = 1e-5 roff = 0.1 von = 0.2 voff= -0.3) .ends note: for further discussion of the pspice model, consult a new pspice sub-circuit for the power mosfet featuring global temperature options ; ieee power electronics specialist conference records, 1991, written by william j. hepp and c. frank wheatley. 18 22 + - 6 8 + - 5 51 + - 19 8 + - 17 18 6 8 + - 5 8 + - rbreak rvtemp vbat rvthr es it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mweak ebreak dbody rsource source 11 7 3 lsource rlsource cin rdrain evthres 16 21 8 mmed mstro drain 2 ldrain rldrain dbreak dplcap eslc rslc1 10 5 51 50 rslc2 1 gate rgate evtemp 9 esg lgate rlgate 20 + - + - + - 6
?2002 fairchild semiconductor corporation FQP45N03L rev. b FQP45N03L saber electrical model rev october 2002 template FQP45N03L n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl = 1.1e-11, rs = 8.9e-3, trs1 = 9e-4, trs2 = 1e-6, xti=2.2, cjo = 7e-10, tt = 8e-11, m = 0.49, n1=1.0 75) dp..model dbreakmod = (rs = 1.1, trs1 = 1e-3, trs2 = -8.9e-6) dp..model dplcapmod = (cjo = 4.5e-10, isl=10e-30, nl=10, m=0.46) m..model mmedmod = (type=_n, vto = 1.9, kp=6, is=1e-30, tox=1) m..model mstrongmod = (type=_n, vto = 2.29, kp = 50, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 1.54, kp = 0.05, is = 1e-30, tox = 1, rs=0.1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -4.0, voff = -.8) sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -.8, voff = -4.0) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.3, voff = 0.2) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.2, voff = -0.3) c.ca n12 n8 = 8e-10 c.cb n15 n14 = 1e-9 c.cin n6 n8 = 1.35e-9 dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod i.it n8 n17 = 1 l.ldrain n2 n5 = 1e-9 l.lgate n1 n9 = 6.24e-9 l.lsource n3 n7 = 3.15e-9 m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1 = 1e-3, tc2 = -7e-7 res.rdrain n50 n16 = 2e-3, tc1 = 1.9e-2, tc2 = 3e-5 res.rgate n9 n20 = 1.9 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 62.4 res.rlsource n3 n7 = 31.5 res.rslc1 n5 n51= 1e-6, tc1 = 1e-3, tc2 =1e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 9.5e-3, tc1 = 1e-3, tc2 =1e-6 res.rvtemp n18 n19 = 1, tc1 = -1.8e-3, tc2 = 1e-6 res.rvthres n22 n8 = 1, tc1 = -2.1e-3, tc2 = -1e-5 spe.ebreak n11 n7 n17 n18 = 31.8 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e-6/160))** 5)) } } 18 22 + - 6 8 + - 19 8 + - 17 18 6 8 + - 5 8 + - rbreak rvtemp vbat rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mweak ebreak dbody rsource source 11 7 3 lsource rlsource cin rdrain evthres 16 21 8 mmed mstro drain 2 ldrain rldrain dbreak dplcap iscl rslc1 10 5 51 50 rslc2 1 gate rgate evtemp 9 esg lgate rlgate 20 + - + - + - 6
?2002 fairchild semiconductor corporation FQP45N03L rev. b FQP45N03L spice thermal model rev 23 october 2002 FQP45N03L_thermal ctherm1 th 6 1.0e-3 ctherm2 6 5 1.5e-3 ctherm3 5 4 1.9e-3 ctherm4 4 3 3e-3 ctherm5 3 2 5e-3 ctherm6 2 tl 2.5e-2 rtherm1 th 6 2.5e-3 rtherm2 6 5 3.5e-3 rtherm3 5 4 5.2e-2 rtherm4 4 3 5e-1 rtherm5 3 2 5.7e-1 rtherm6 2 tl 6.9e-1 saber thermal model saber thermal model FQP45N03L_thermal template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 1.0e-3 ctherm.ctherm2 6 5 = 1.5e-3 ctherm.ctherm3 5 4 = 1.9e-3 ctherm.ctherm4 4 3 = 3e-3 ctherm.ctherm5 3 2 = 5e-3 ctherm.ctherm6 2 tl = 2.5e-2 rtherm.rtherm1 th 6 = 2.5e-3 rtherm.rtherm2 6 5 = 3.5e-3 rtherm.rtherm3 5 4 = 5.2e-2 rtherm.rtherm4 4 3 = 5e-1 rtherm.rtherm5 3 2 = 5.7e-1 rtherm.rtherm6 2 tl = 6.9e-1 } rtherm4 rtherm6 rtherm5 rtherm3 rtherm2 rtherm1 ctherm4 ctherm6 ctherm5 ctherm3 ctherm2 ctherm1 tl 2 3 4 5 6 th junction case
rev. i1 trademarks the following are registered and unregistered trademarks fairchild semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms acex? activearray? bottomless? coolfet? crossvolt? dome? ecospark? e 2 cmos? ensigna? fact? fact quiet series? fast ? fastr? frfet? globaloptoisolator? gto? hisec? i 2 c? implieddisconnect? isoplanar ? littlefet ? microfet ? micropak ? microwire ? msx ? msxpro ? ocx ? ocxpro ? optologic ? optoplanar ? pacman ? pop ? power247 ? powertrench ? qfet ? qs ? qt optoelectronics ? quiet series ? rapidconfigure ? rapidconnect ? silent switcher ? smart start ? spm ? stealth ? supersot ? -3 supersot ? -6 supersot ? -8 syncfet ? tinylogic ? trutranslation ? uhc ? ultrafet ? vcx ? across the board. around the world. ? the power franchise ? programmable active droop ? datasheet identification product status definition advance information formative or in design this datasheet contains the design specifications for product development. specifications may change in any manner without notice. preliminary first production this datasheet contains preliminary data, and supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. no identification needed full production this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. obsolete not in production this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only.
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